Logic analyzers are digital data acquisition instruments that allow a user to acquire and analyze digital data from a large number of logic signals, such as all of the address, data, and control signals associated with a microprocessor. Each logic signal is compared to a logic threshold or thresholds and resolved into one of two logic states, high or low, one or zero, true or false. The behavior of groups of these signals can then be monitored to analyze the behavior of the circuitry under test.
The time at which the state of the logic signals under analysis is resolved into binary form is determined by a clock signal. If this clock signal is generated by the logic analyzer and is independent of the system under test, the acquisition is said to be "asynchronous". If the clock signal is derived from the system under test so as to bear a predetermined timing relationship to part of the activity within that system, the acquisition is said to be "synchronous". Data that is originally synchronous to the user's system clock must be resynchronized to the internal clock of the logic analyzer for further processing. U.S. Pat. No. 4,949,361 to Jackson for "Digital Data Transfer Synchronization Circuit and Method" hereby incorporated by reference, describes circuitry for accomplishing this task very efficiently.
Typically, asynchronous data acquisition is relatively rapid and is used for analyzing the "timing" of circuit hardware. And, synchronous data acquisition is typically relatively slower and is used for analyzing the "state" of the system during software execution. U.S. Pat. No. 4,425,643 to Chapman et al. for a "Multi-Speed Logic Analyzer", hereby incorporated by reference, describes a logic analyzer with two sections capable of operating in conjunction with two different clocks. This type of architecture permits coordinated state and timing analysis.
Once data is acquired from two different clock signals (also know as "timebases") that are asynchronous to each other and therefore "unrelated", methods must be found to make their relative timing relationships available to the operator of the logic analyzer. U.S. Pat. No. 4,558,422 to DenBeste et al. for a "Digital Signal Sampling System with Two Unrelated Sampling Timebases", and U.S. Pat. No. 4,578,666 to Anderson for a "Method of Comparing Data with Asynchronous Timebases", both hereby incorporated by reference, both describe ways of handling data so that an accurate display of timing relationships is presented to the operator.
Another approach to keeping track of the sampling time associated with different events is the use of "timestamps". Timestamps are a count that is stored when each sample is acquired, and which can then later be used for a variety of purposes. U.S. Pat. No. 4,731,768 to Easterday for "Autoranging Time Stamp Circuit", hereby incorporated by reference, describes one approach to timestamp generation.
The data in the system under analysis may suffer from a variety of defects that distinguish it from theoretically ideal digital data, i.e., data that goes from one stable and well defined logic state to another in an appropriate transition. Data may contain "glitches", or be unstable in some other way, or the data transition may suffer from slow rise or fall times, or exhibit other less-than-ideal behaviors. U.S. Pat. No. 4,353,032 to Taylor for "Glitch Detector", hereby incorporated by reference, describes glitches and a circuit for capturing information about them. U.S. Pat. No. 4,968,902 to Jackson for "Unstable Data Recognition Circuit for Dual Threshold Synchronous Data", hereby incorporated by reference, describes circuitry for detecting when one or more signals under analysis are not behaving properly. And, U.S. Pat. No. 5,043,927 which is also to Jackson for "Digital Signal Quality Analysis Using Simultaneous Dual-Threshold Data Acquisition", hereby incorporated by reference, describes a method for finding a variety of signal anomalies in a repetitive signal using dual thresholds in a succession of measurements.
Since logic analyzers acquire signals across a large number of channels simultaneously, and the signal paths through the input circuitry of the logic analyzer or the probes used to connect to the user's system may not be all exactly equivalent electrically, the propagation times of signals passing through these different paths may not be all the same. When this occurs, one signal is said to exhibit "skew" in relation to a another signal. U.S. Pat. No. 4,646,297 to Palmquist et al. for "Skew Detector", hereby incorporated by reference, describes a circuit for detecting this condition. U.S. Pat. No. 4,481,647 to Gombert et al. for "Method and Apparatus of Compensating for Variations in Signal Propagation Time Existing Within the Channels of a Multi-Channel Device", hereby incorporated by reference, describes means for correcting skew errors.
The "resolution" of a logic analyzer is typically the same as the acquisition clock period, e.g., 10 ns for a 100 MHz clock. U.S. Pat. No. 4,979,177 to Jackson for "Enhanced Counter/Timer Resolution in a Logic Analyzer", hereby incorporated by reference, describes a logic analyzer with the ability to use two phases of the system clock to acquire data and then maintain the resulting improved resolution as the data is manipulated internally using a single phase clock. The result is an effectively doubled resolution, e.g., 5 ns for a 100 MHz clock. Another approach is described in U.S. Pat. No. 4,777,616 to Moore et al. for "Increased Resolution Logic Analyzer Using Asynchronous Sampling", hereby incorporated by reference. This approach relies on repeatedly sampling a repetitive signal asynchronously to increase the effective resolution.
Obviously, the most straightforward way to increase resolution is to increase the frequency of the acquisition clock signal itself. One of the obstacles that is encountered with this approach is the speed limitations of the acquisition memory. U.S. Pat. No. 4,903,240 to Von Flue for "Readout Circuit and Method for Multiphase Memory Array", hereby incorporated by reference, describes a scheme for demultiplexing the input signal data into an array of memories and circuitry for reading out the contents of those memories.
The fast acquisition of data is even more challenging when the analog level of the input signal must be determined, rather than just its relationship to a logic level threshold. This challenge is always present in high speed analog oscilloscopes such as the one whose front end is described in U.S. Pat. No. 5,144,525 to Saxe et al. for "Analog Acquisition System Including a High Speed Timing Generator", hereby incorporated by reference. Another high speed, fast-in slow-out (FISO) acquisition system is described in U.S. Pat. No. 4,271,488 to Saxe for a "High-Speed Acquisition System Employing an Analog Memory Matrix", hereby incorporated by reference.
In U.S. Pat. No. 5,144,525 each cell in the array is selected sequentially for sampling at a very rapid rate. Rows within this array of cells are selected by slow timing signals generated by a slow shift register, while individual cells within each row are selected by fast sample and hold signals, generated in a variety of alternative ways.
A variety of the methods for generating rapidly occurring hold signals that are discussed in the U.S. Pat. No. 5,144,525 patent. However, even the fastest and most adjustable of these methods have limitations in their speed and adjustability. Co-pending U.S. patent application Ser. No. 07/824,434 (assignee docket number USA 5429) to Kogan for "High Speed Sample and Hold Signal Generator", hereby incorporated by reference, provides an improved sample and hold signal generator with very short delay intervals between successive sample-to-hold signal transitions and adjustability in both the timing of individual transitions relative to a reference timing signal and in the collective delay of a whole row of fast timing signals.
All synchronous digital circuitry requires a certain degree of stability of its inputs in order to guarantee appropriate and reliable behavior of its outputs. The time that inputs must be stable before a synchronizing event in order to assure proper operation is known as "setup time", while the time that inputs must be stable after the synchronizing event to assure proper operation is known as "hold time". A logic analyzer also has setup and hold times of its own. Normally, the setup time of a logic analyzer is as short as possible and its hold time is zero. Ideally, this setup and hold time "window" would be adjustable so that it could be positioned as the user desires.
A conventional logic analyzer typically does some processing of a user's clock signal before using it to acquire synchronous data. Since this processing takes some time, the data signals that are to be clocked also must be delayed in order to position the setup and hold time window where it belongs, Putting delay lines on every channel adds a lot to the price of a logic analyzer. Moreover, equalizing the resulting delays can add additional expense and complexity. If every delay line is adjustable, channel-to-channel skew can be minimized and the setup and hold window can be minimized, and even moved relative to the acquisition clock signal. However, putting adjustable delay lines on every channel is quite expensive. Nonetheless, this is the approach that has frequently been employed to make a logic analyzer with suitable specifications. Since the setup and hold time for a group of channels is only as good as the worst of those channels, channel-to-channel skew degrades the logic analyzer's overall setup and hold time performance as well as having a variety of other detrimental effects.
Recently, at least one manufacturer of logic analyzers (Hewlett-Packard) has adopted synchronous oversampling of input signals in one of its logic analyzers, the HP 16517A. (It is believed that this approach was first developed by Outlook Technology, now part of Biomation, in the early 1980's.) In this approach a user's clock signal is used to control a phase lock loop (PLL) that is tuned to produce an acquisition clock signal at a frequency that is a multiple of the user's clock frequency. This approach allows a better view of fine timing differences between channels, but it suffers from several major limitations relative to the present invention. Because of the use of PLL, the user's clock signal must be periodic and above a minimum frequency, and the logic analyzer that uses it must be implemented in a high-speed, higher-cost, lower-density technology to support that speed. Any jitter in the user's clock signal causes sampling errors in the data acquired. And, because the logic analyzer's internal synchronization is also controlled by the user's clock, any time measurements must be indirect, i.e., the product of a clock count and a measured average period of the user's clock signal.